In device fabrication, insulating, semiconducting, and conducting layers are formed on a substrate. The layers are patterned to create features and spaces. The minimum dimension or feature size (F) of the features and spaces depend on the resolution capability of the lithographic systems. The features and spaces are patterned so as to form devices, such as transistors, capacitors, and resistors. These devices are then interconnected to achieve a desired electrical function. The formation and patterning of the various device layers are achieved using conventional fabrication techniques, such as oxidation, implantation, deposition, epitaxial growth of silicon, lithography, and etching. Such techniques are described in S. M. Sze, VLSI Technology, 2nd ed., New York, McGraw-Hill, 1988, which is herein incorporated by reference for all purposes.
Random access memories, such as dynamic random access memories (DRAMs), comprise memory cells that are configured in rows and columns to provide storage of information. One type of memory cells includes, for example, a transistor connected to a trench capacitor. Typically, the capacitor plate, which is connected to the transistor is referred to as the "node" when activated, the transistor allows information to be read or written into the capacitor.
Continued demand to device miniturization to have resulted in DRAMs with smaller feature size and cell area. For example, reduction of the conventional cell area of 8F.sup.2 towards and below 6F.sup.2 have been investigated. However, the fabrication of such small feature and cell sizes creates oxidation stress, where the node is isolated from the substrate. The oxidation stress, in turn, creates dislocations which increases the node junction leakage current. Such increases in node leakage current adversely impacts the performance and operability of the memory cells.
From the above discussion, it is apparent that there is a need to reduce oxidation stress that results during the fabrication of devices.